IEEE Seattle Section Feb 2017 ExCom meeting and CAS/PEL Technical presentation “A Scalable High-density ECoG Recording Architecture for Bi-directional Brain Computer Interfaces”

You are cordially invited to listen to a CAS & PEL joint presentation by Dr. Visvesh Sathe from the University of Washington. The presentation will be immediately followed by the Seattle Section Executive Committee February 2017 meeting. As usual we will provide some food and soft drinks.

“A Scalable High-density ECoG Recording Architecture for Bi-directional Brain Computer Interfaces”

Abstract : Bi-directional Brain Computer Interfaces (BBCI), systems capable of recording from, and providing stimulus to the nervous system offer great promise for helping patients with motor defects, and serve as a critical tool for the understanding of the Brain. It is anticipated that future BBCI systems will require processing over a thousand  channels between stimulus and recording, while maintaining power, volume, and precision constraints. Much progress has been made in recent years to advance the state-of-the-art in integration and power dissipation. However, existing methods, largely extensions of traditional approaches to Analog-Front-End (AFE) design do not scale well to the new thousand channel paradigm. Further, the problem of canceling artifacts of stimulation during recording are challenges-Significant improvement is required in differential artifact cancellation, and common mode cancellation remains an open problem. In this talk, I will discuss recent work in my group focusing on circuit-architectures that are focused in three areas (1) scalability in frequency, channel-count, process-technology (2) Exploiting the statistics of neural signals to meet challenging system level performance ~(e.g. 15b ADC resolution) using simpler, robust, low-power circuits and (3) A novel switched-capacitor technique that achieves artifact cancellation. Silicon measurements of a single-channel prototype in 65nm CMOS will be presented.

Bio: Visvesh S. Sathe received the B.Tech degree from the Indian Institute

of Technology Bombay in 2001, and the M.S and Ph.D. degrees from the University

of Michigan, Ann Arbor in 2004 and 2007, respectively. He is currently an Assistant

Professor at the University to Washington. Prior to joining the faculty at UW, he served

as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD,

where his research focused on inventing and developing new technologies for energy-efficient

computing. Prof. Sathe led the research and development effort at AMD that resulted in the

first-ever resonant-clocked commercial microprocessor. Several of his inventions in the area

of high performance digital circuits and adaptive clocking for supply noise mitigation have been

incorporated into current and next generation microprocessors. His current research is focussed

on digital and mixed-signal circuit-architectures for energy efficient computing and biomedical

circuits, including next-generation clocking and integrated voltage regulation.