Week of Events
Sunday, December 9, 2018
No events on this day.
Monday, December 10, 2018
No events on this day.
Tuesday, December 11, 2018
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December 11, 2018 -Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond
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December 11, 2018 -IEEE Seattle Excom Dece 2018
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December 11, 2018 -IEEE Seattle Section Excom
Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond
Co-sponsored by: CH06129 CAS04 ABSTRACT The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity. Speaker(s): Dr. Alvin Loke, Agenda: ABSTRACT The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity. Location: Room: 1919 Bldg: 99 14820 Northeast 36th Street Redmond, Washington 98052
IEEE Seattle Section Excom
Excom Location: Room: 1919 Bldg: 99 14820 Northeast 36th Street Redmond, Washington 98052
Wednesday, December 12, 2018
No events on this day.
Thursday, December 13, 2018
No events on this day.
Friday, December 14, 2018
No events on this day.
Saturday, December 15, 2018
No events on this day.