Summary: Approximately 1.1 billion people worldwide lack access to the electricity grid. This form of energy poverty disproportionately afflicts those living in less economically developed countries, primarily in Sub-Saharan Africa and southern Asia. Achieving universal electrification through grid extension is optimistically decades away and might never be a viable option in rural areas. Instead, many communities will rely on off-grid electricity solutions in the form of renewable energy-powered microgrids. This presentation describes the role of microgrids and other off-grid solutions in providing electricity access. Technical design examples from microgrids in Zambia will presented. Parking: Please park in front lot, free & open space parkingPSE employees: please park in gated area to maximize open parking space Speaker(s): Dr. Henry Louie, Daniel Nausner Agenda: 6:00 pm – Networking and Light Refreshments 6:45 pm – Introductions and Technical Talk and Demo 8:00 pm – Adjourn Location: Room: Columbia & Bennett Room 13230 SE 32nd St Bellevue, Washington 98005

The heavier loading of existing power systems infrastructure along with the utilization of significant amounts of renewable energy sources pose new challenges to the power systems real-time operational security, defined by NERC as the ability of electric power grids to withstand sudden, unexpected disturbances such as short circuit faults. Therefore, developing secure and dependable protection schemes ranging from digital protection algorithms to wide area protection schemes that enhance real-time operational security and fault-tolerance of power systems is of crucial need as they would translate to several billions of dollars in annual savings in the U.S. alone. This talk first presents a brief overview of our System of Systems (SoS) approach for addressing new challenges of protection of modern cyber-physical power systems with high penetration of renewable energy sources. The proposed protection and emergency control strategies are implemented at multiple timescales and are deployed at different locations spanning from the interface of renewable energy sources (milliseconds timescale), to digital protective relays distributed throughout the power grid (fractions of a second timescale) and wide area protection systems at control centers (seconds to minutes timescale). The talk then discusses a cascading failure protection strategy, consisting of digital protection algorithms and Special Protection Systems (SPS), that enhances power systems fault tolerance and resilience against cascading failures.   Speaker(s): Saeed, Location: Seattle, Washington

Co-sponsored by: IEEE Seattle section, Computer Society and Signal Processing Society Please come to enjoy our Holiday Banquet,  Delicious Food, Good Wine, Pleasant Companies, Stimulating Keynote                  and Inspiring Discussions….. Keynote: Timothy Lee IEEE USA Region 6 Director - elect Guest Speaker: Aline D. McNaull, Legislative Representative, IEEE-USA               The event will be held at Mandarin Buffet and Grill. There are over 800 delectable dishes for your pleasure,    Mongolian bar, sushi, crab, steamers, seafood, dessert, salad, chocolate fountain, ice cream and more.... Speaker(s): Tim Lee, Aline McNaull Agenda: November 30th, 2018 6 pm  Reception 6:30 pm Dinner, 7:00 Pm Keynote by Timothy Lee, Region 6 Director elect 7:30 pm  Speech by Aline McNaull, Legislative Representative, IEEE-USA Location: Room: Banquet Room Bldg: Mandarin Buffet and Grill 14850 NE 24th St Redmond, Washington 98052

The energy storage analytics team at PNNL is currently evaluating storage systems with a combined 25 MW / 103 MWh of capacity at twelve sites across the U.S. We are evaluating lithium-ion and vanadium redox flow batteries in Washington State, demand response programs in Hawaii, microgrids in Massachusetts, and pumped storage hydro systems in Washington State, California, New York, and Hawaii. We have developed a framework and a set of tools for evaluating the economic benefits of storage systems, characterizing their performance during economic operation, and developing real-time control systems in order to enhance the benefits actually achieved once the systems are installed. This presentation will provide an overview of the lessons learned through a number of recent engagements on each of these topics and will demonstrate how these lessons are being applied in filling gaps in the industry knowledge base.   Speaker(s): Patrick, Kendall Location: Seattle, Washington

Co-sponsored by: CH06129 CAS04 ABSTRACT The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.  Speaker(s): Dr. Alvin Loke, Agenda: ABSTRACT The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.  Location: Room: 1919 Bldg: 99 14820 Northeast 36th Street Redmond, Washington 98052

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Excom Location: Room: 1919 Bldg: 99 14820 Northeast 36th Street Redmond, Washington 98052