Room: Room ECE 269, Bldg: Electrical and Computer Engineering Building, 185 Stevens Way, Seattle, Washington, United States, 98195

Title: Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation Abstract: Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration. Speaker(s): Tetsuya, Room: Room ECE 269, Bldg: Electrical and Computer Engineering Building, 185 Stevens Way, Seattle, Washington, United States, 98195